This invention relates to complementary field-effect transistor integrated circuit structures, and more particularly to the elimination of parasitic pnpn elements in such structures.
Integrated circuits using complementary metal-oxide-semiconductor (CMOS) transistors are well known. Such circuits which combine both p- and n-channel enhancement mode transistors on the same substrate chip offer high performance, low standby power dissipation, high noise immunity and single power supply operation. Owing to these desirable characteristics, CMOS circuits are now widely used in a variety of applications such as random access memories and microprocessors. At present, CMOS circuits having extremely high packing density of devices on a single chip are being developed.
One problem with CMOS circuits is that parasitic active elements which are inherently a part of conventional CMOS structures can cause very large currents to flow between the power supply terminals of the circuit. In a conventional CMOS structure, p-channel devices are formed in the surface of an n-type substrate wafer and n-channel devices are formed in the surface of a p-type "tub" region formed in the substrate. When a p-channel device and an n-channel device are placed in close proximity, the p-type source and drain regions of the p-channel device, the n-type bulk substrate region, the p-type bulk "tub" region and the n-type source and drain regions of the n-channel device form a pnpn structure which can operate as a silicon-controlled rectifier (SCR). This parasitic SCR can be triggered into a self-sustained high conductivity state, known as the latchup state, by noise signals of appropriate polarity and magnitude applied to the source or drain regions of the transistors. For example, latchup can be triggered by a noise transient pulse having a voltage whose magnitude exceeds that of the power supply voltage and which is picked up by an external terminal of a CMOS circuit. Once triggered, the parasitic SCR remains in the latchup state until the power supply voltages of the CMOS circuit are removed or are greatly reduced. The result of latchup is temporary malfunction of the CMOS circuit or, in some cases, permanent circuit damage.
Another characteristic of the latchup problem is that as the spacing between the p- and n-channel devices and the dimensions of the devices themselves are made smaller in order to achieve a higher packing density, the parasitic SCR becomes more easily triggered. Consequently, as the packing density of a conventional CMOS circuit is increased, the circuit becomes more susceptible to latchup. Therefore, the latchup problem also imposes a limitation on the maximum packing density achievable with conventional CMOS structures.
Heretofore, known solutions to the latchup problem in CMOS circuits have been directed towards making the parasitic SCR more difficult to trigger rather than towards totally eliminating the SCR structure itself. These solutions have included the use of heavily doped p-type and/or n-type guard regions for separating the p-channel devices from the n-channel devices, the use of a heavily doped p-type buried layer beneath the p-type "tub" region, and the use of an n-type epitaxial layer on a heavily doped n-type substrate as starting material for the CMOS circuit.
However, the increase in trigger threshold level for the parasitic SCR provided by each of the above techniques are offset by a decrease in the trigger threshold level as device spacings and dimensions are reduced to achieve a higher packing density. Therefore, while each of the previously known solutions provides adequate latchup protection for CMOS circuits at the present packing density they are less adequate for the circuits of higher packing density currently being developed. Thus, a need clearly exists for a CMOS structure which is incapable of latchup at any device packing density.